MicroEJ Architecture


MicroEJ Architecture features the MicroEJ Core Engine built for a specific instructions set (ISA) and compiler.

The MicroEJ Core Engine is a tiny and fast runtime associated with a Scheduler and a Garbage Collector.

MicroEJ Architecture provides implementations of the following Foundation Libraries :

  • EDC: Embedded Device Configuration.
  • BON Beyond Profile (see [BON]).
  • SNI Simple Native Interface ([SNI]).
  • SP Shielded Plug ([SP]).
  • KF Kernel & Features ([KF]).

The following figure shows the components involved.

MicroEJ Architecture Runtime Modules: Tools, Libraries and APIs

MicroEJ Architecture Modules

Three Low Level APIs allow the MicroEJ Architecture to link with (and port to) external code, such as any kind of RTOS or legacy C libraries:

  • Simple Native Interface (see [SNI])
  • Low Level MicroEJ Core Engine (see LLMJVM)
  • Low Level Shielded Plug (see LLSP)

Naming Convention

MicroEJ Architecture files ends with the .xpf extension, and are classified using the following naming convention:

  • ISA: instruction set architecture (e.g. CM4 for Arm® Cortex®-M4, ESP32 for Espressif ESP32, …).
  • TOOLCHAIN: C compilation toolchain (e.g. CM4hardfp_GCC48).
  • UID: Architecture unique ID (e.g. flopi4G25).
  • VERSION: module version (e.g. 7.12.0).
  • USAGE = eval for evaluation Architectures, prod for production Architectures.

For example, MicroEJ Architecture versions for Arm® Cortex®-M4 microcontrollers compiled with GNU CC toolchain are available at https://repository.microej.com/modules/com/microej/architecture/CM4/CM4hardfp_GCC48/flopi4G25/.

See MicroEJ Architecture Import for usage.